This invention relates to a data bus circuit of a signal processing device.
Generally, various types of signal processing device are composed of a plurality of functional blocks. These functional blocks are coupled with a certain common bus, and through this common bus, data having a certain data width processed in one functional block (for example, 16-bit width, 32-bit width, 64-bit width) is supplied to another functional block.
In the construction of a conventional bus circuit, since data is fed into an input port circuit by continually alternating the large parasitic capacity of the data bus line in full between the supply voltage and grounding voltage, it is difficult to realize a high speed data transfer cycle.